Conventional semiconductor manufacturing processes typically utilize a planar process wherein semiconductor structures such as transistors, capacitors, diodes, etc., were formed in a horizontal manner on the face of the semiconductor substrate. As the density of semiconductor structures increase, the semiconductor manufacturers merely "scale down" the structures by using advanced lithography techniques. However, as line widths have decreased, available processing techniques have proved to be a limiting factor, especially when the line widths fall to sub-micron dimensions. Thus, the need for increased density, especially in the memory area, still existed.
To increase the density of an integrated circuit beyond the limits of the available photolithography techniques, vertically integrated structures have been utilized. These structures typically utilize one of two techniques, a first technique for building the structure upward from the face of the semiconductor substrate, and a second technique for building the structure vertically down into the substrate. In the first technique, various epitaxial layers are grown on top of a base substrate with structures fabricated within the intermediate epitaxial layers. The disadvantage to this is that it is difficult to form an epitaxial layer at a later time while still preserving the underlying structure. In the vertical structure formed downward into the substrate, trench etching techniques have been utilized wherein a trench is etched into the substrate and various structures formed on the sidewalls of the trench. This is typically utilized for dynamic random access memory cells wherein the capacitor can be formed along the trench. Further, the vertical structures have been realized wherein the transistor is formed on the sidewall of the trench. However, these have typically used amorphous polysilicon which provides rather poor leakage characteristics for a transistor.